FPGA implementation of a flexible synchronizer for cognitive radio applications
Farid Shamani, Roberto Airoldi, Tapani Ahonen, Jari Nurmi · 2014
This paper presents a flexible timing synchronization scheme implemented on an Altera Stratix-V Field Programmable Gate Array (FPGA) device. The core content of the synchronizer is based on a reconfigurable Finite Impulse Response (FIR) filter which performs as a multicorrelator on demand. In concept of flexibility, the synchronizer is able to reconfigure its FIR filter block with Partial Reconfiguration (PR) feature, while the rest of the design is operating. Different synchronization architectures have been evaluated for the design, including MultiplierLess(ML)-based multicorrelator as well as Transposed, Sequential, Parallel and Pipelined-Parallel direct form FIR filters. All the developed architectures are compared to each other in terms of power consumption, chip area, maximum frequency. Synthesis results show that the ML-based multicorrelator achieves 93% better performance in terms of dynamic thermal power dissipation. The ML algorithm also decreases the logic utilization down to 1% of the chip area while the MAC-based architectures utilize almost 7% of the device.