A CMOS 100MHz Microprocessor
Joseph Schutz · 1991
A CMOS 100MHz, 1.2-million-transistor microprocessor in 80=² hasbeen developed in conjunction with a three-metal layer sub-micron technology. This microprocessor utilizes a previous architecture consisting of a floating-point unit and an 8kB combined instruction-and-datacache memory depicted in the die photo of Figure 1.* This implementation emphasizes two areas. First, new design methodology and CAD tools exploit the interconnectivity afforded by the triple-metal proc ess, resulting in high packing density and internal speed. Second, clock synchronization techniques and flexible I/0 timing permit high-speed chip-to-chip connections essential in a high-performance CPU cache core. The microprocessor re ported here forms the nucleus of a high-performance CPU cache core module. This paper describes the design methodol ogy, circuit techniques, process technology, and the overall results achieved.