A 320ps access, 3GHz cycle, 144Kb SRAM macro in 90nm CMOS technology using an all-stage reset control signal generator
Hirofumi Akiyoshi, Haruo Shimizu, Tetsuro Matsumoto, K. Kobayashi, Yasuhiro Sambonsugi · 2003
A 320ps access, 3GHz cycle, 144kb SRAM macro was developed in 90nm CMOS technology. This macro adopts an all-reset control signal generator and hierarchical bit line. These techniques enable both the cycle and access speeds to be 1.7 times faster than those available with 130nm technology.