An RTL Verilog processor
H. Jamal, Sheroz Khan, Fazal Hameed, S. Saeed, M. Pasha · 2003
This paper presents a processor that efficiently executes Verilog code written at Register Transfer Level (RTL). It is a RISC type processor that performs the parallel execution of multiple procedural blocks of Verilog HDL. This results in a very significant saving of simulation time. The simulation time taken by the software based simulation in terms of clock cycles on a normal Pentium Processor is Million times more than taken by this processor built on an FPGA.