Building blocks for a temperature-compensated analog VLSI neural network with on-chip learning
A.J. Montalvo, R.S. Gyurcsik, John J. Paulos · 2002
Synapse, neuron, and weight increment circuits for a high density, temperature-compensated analog VLSI neural network are introduced. The synapse circuit, which consumes 4500 /spl mu/m/sup 2/ in a 2-/spl mu/m technology, uses hybrid dynamic and non-volatile weight storage. Dynamic memory allows fast learning while non-volatile memory allows reliable long-term storage and low power dissipation. Measured test results for the synapse are presented. The synapse includes a weight increment circuit that adds offset of only 1 part in 16 bits, thus allowing analog-domain on-chip learning using a weight perturbation algorithm. Simple bias circuits cancel temperature dependent parameters in the synapse-neuron transfer function, allowing reliable operation in the temperature range -55 C to 125 C.>