A power efficient register file architecture using master latch sharing
Marek Wróblewski, M. Mueller, Andreas Wortmann, Sandra Simon, W. Pieper, Josef A. Nossek · 2003
This paper introduces a method of reducing area and power consumption of a synthesizable register file by using a single master latch shared by a number of slaves. It investigates potential timing problems and discusses possible solutions. Presented simulation results show that, depending on the size of the register file, reduction of power consumption of more than 50% is achievable.