C-NNAP-a parallel processing architecture for binary neural networks
J.V. Kennedy, J. Austin, Robert C. Pack, Bruce Cass · 2002
This paper describes the C-NNAP machine, a MIMD implementation of an array of ADAM (advanced distributed associative memory) binary neural networks, primarily designed for image processing. C-NNAP comprises an array of VME cards each containing a DSP, SCSI controller and a new design of the sum and threshold (SAT) peripheral processor. The SAT processor is a dedicated hardware implementation that performs binary neural network computations. The SAT processor yields a potential speed-up of between 108 times to 182 times that of the current DSP with its dedicated coprocessor. C-NNAP in association with the SAT provide a fast, parallel environment for performing binary neural network operations.