PREP benchmarks for programmable logic devices
D. McCarty, D. Faria, Peter Alfke · 2002
The authors describe a set of benchmark circuits and implementation methodology for measuring logic capacity and speed performance in programmable logic devices (PLDs). PLDs include complex PLDs and field programmable gate arrays (FPGAs). The PREP (Programmable Electronic Performance Corporation) benchmarks were developed for users of PLDs to evaluate different architectures and devices for logic capacity and speed performance using common logic functions and a standard methodology.