Super-compact shared-cache memories with low power consumption for multi-issue single chip processors
Koji Kishi, Takayuki Gyohten, Jongshik Kim, Hans Jürgen Mattausch, Yuki Tatsumi, S. Nara · European Solid-State Circuits Conference · 2000
On-chip shared-cache memories with high access-bandwidth are desirable for single-chip processors with parallel execution capability of multiple instructions. For this application a new area-efficient hierarchical architecture [1,2] is ideally suited, because the necessary large storage capacities as well as sufficiently low power consumption can be realised in addition to the high access-bandwidth. A 4-port hierarchical SRAM with 32 Kbit storage-capacity was fabricated in a 0.5µm CMOS technology as a test-chip for the data-storage part of the cache. The chip is completely functional and could realise the predicted area reduction. A conventional 4- port SRAM in the same technology would already consume 36% more area for just the 4-port storage cells without any peripheral circuits. Power-consumption is proportional to the port number, but increases very slowly as a function of storage capacity.