High speed arithmetic design using CPL and DPL logic
Peter Y. K. Cheung, M.V. Scotti, Jeffrey Blake, B. W. Brewer, Richard Grisenthwaite, D. Hitchcox, Paul Shepherd · 1997
PRML disk drive read channels have been developed delivering bit rates of 140-250Mbits/s in 0.6-0.35µm technologies. These require high speed low power digital arithmetic circuitry. Investigations have been carried out to find an optimum device level design style, which has the characteristics of high speed with minimum power. The CPL (Complementary Pass Logic) design style was used successfully in the read channel developments, but it is shown that DPL (Double Pass Logic) may be faster and, more significantly, is easier to map and optimise at device level than CPL. This is significant in improving optimisation and reducing design time.