A 0.18/spl mu/m CMOS implementation of an area efficient precise exception handling unit for processing-in-memory systems
Sumit Dharampal Mediratta, Craig S. Steele, R. Singh, Jeff Sondeen, Jeffrey T. Draper · 2004
This paper describes the implementation of theexception handling mechanism in the second prototype version of the Data-Intensive Architecture (DIVA) processing-inmemory (PIM) chip. This implementation features architectural simplicity, low area (54289 p 2 ) , delay (2.643 nanosecond) and power consumption (7.6 milliwatts), and effective hardware support for complex cases of exception handling. This work provides a description of handling memory-access, execution and communication-related exceptions in an area- and powerefficient manner, which are key design specifications for DIVA. The current implementation has been tested by verifying various exceptions on DIVA-I1 PIM chips running at 140MHz in the memory system of a HP Itanium2-based Long’s Peak server. The generic nature of the DIVA exceptions and their classification makes the current implementation suitable and easy for use in diverse microarchitectures with little modification.