High-speed serial communication with error correction using 0.25 μm CMOS technology
T. Suutari, Jouni Isoaho, H. Tenhumen · 2002
In this paper we propose a novel design for an autonomous high-speed serial off and on-chip communication system which incorporates impedance tuning, error correction with a packet transfer and a parallel asynchronous interface. The constructed transmitter-receiver pair has throughput of 5 Gbit/s. With error correction and packet transfer overhead accounted for this construct has bandwidth of 500 < bytes/s. The circuit has been simulated using HSpice with 0.25 μm TMSC CMOS technology.