Efficient ASIC implementation of a real-time depth mapping stereo vision system
Markus Kühn, Sebastian Möser, O. Isler, Frank K. Gürkaynak, Andreas Peter Burg, N. Felber, Hubert Kaeslin, Wolf Fïchtner · 2006
This paper presents a fast and area-efficient implementation of a real-time stereo vision algorithm for spatial depth mapping. The design combines two well-known area-based approaches to stereo matching and includes an occlusion detection method. Hardware efficiency is achieved by storing only partial images on-chip, avoiding full-sized frame buffers. A low-latency dataflow-oriented structure makes it possible to process 256/spl times/192 pixel. Input streams with a rate in excess of 50 frames per second, amounting to more than 54 million pixel /spl times/ disparity measurements per second (PDS) (for a 25-pixel disparity range), or roughly 18 GOPS. The design has been integrated in a 0.25 /spl mu/m standard CMOS technology and occupies an area of less than 3 mm/sup 2/.