Performance tradeoffs in multistreamed superscalar architectures
Mauricio J. Serrano · 1994
Superscalar processors employ multiple functional unit designs that can dispatch several instructions every cycle. Two factors limiting the number of instructions dispatched per cycle are: (1) the number of functional units available (hardware), and (2) the amount of parallelism in the workload (software). While the number of functional units determines the peak throughput of a processor, the instruction-level parallelism determines the actual performance obtained. Data dependencies and control breaks constrain instruction-level parallelism resulting in a sustained system performance that is well below the peak. The ability to execute simultaneously multiple instruction streams, referred to as multistreaming, significantly increases the number of independent instructions that can be issued in a cycle. A multistreamed, superscalar processor can dispatch instructions from multiple streams simultaneously. Each stream context is stored internally. The processor adjusts the scheduling policy as the workload changes to maximize throughput. This dissertation explores a methodology for the design of a distributed multistreamed-superscalar processor that addresses instruction issue, implementation of precise interrupts, speculative execution, scheduling, and cache sharing. One of the goals of the design of a processor architecture is to minimize the number of global interconnections and reduce the need for clock synchronization. Variants in the design are possible because of tradeoffs that can be done in the design. We explore several problems present in multistreamed architectures and discuss possible solutions. We present an analytic model to estimate the overall performance of multistreamed architectures. The model uses simple workload and architectural descriptions that are obtained using commonly available tools. The model produces instructions executed per cycle (IPC) as the number of streams is varied.