Pairing and ordering to reduce hardware complexity in cascade form filter design [digital filters]
Hyeong‐Ju Kang, Incheol Park · 2003
This paper presents an algorithm that explores all the combinations of sub-modules in the cascade form filter to reduce hardware complexity under design constraints. Though the cascade form structure has freedom in pairing and ordering of its sub-modules, the hardware complexity is subject to the pairing and ordering if optimization based on the multiplier block concept is applied. The proposed algorithm selects the pairing and ordering that results in the minimal hardware complexity among all the cases that satisfy the frequency response specification. To cope with the case that the objective filter has many taps and the exploration time is too long, a clustering method is also developed. Experimental results on several filters show that the proposed algorithm reduces the hardware complexity by about 10% on average, while satisfying the filter specification.