A routing testing of a VLSI massively parallel machine based on IEEE 1149.1
C. Aktouf, Ch. Robach, A. Marinescu · 2002
A practical testing strategy is presented for locating faults occurring on both cells' routing parts and internal physical lines within a 2D massively parallel machine. We present first an approach which does not consider all practical constraints. Then, an approach based on IEEE 1149.1 standard is studied and its efficiency is illustrated. The results obtained are given.