A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing
Jianchun Li, C. Papachristou, Raj Shekhar · 2004
This paper deals with the reconfigurable SoC (system-on-chip) architecture and a 3D caching scheme targeted to Virtex II Pro FPGAs, to accelerate a broad range of 3D medical imaging algorithms. To achieve high computational bandwidth, architectural parallelisms are exploited at three different levels: brick operation cycle, multiple parallel data-stream processing and deep pipeline architecture for data-stream processing.