The Potential for Thread-Level Data Speculat ion in Tight ly-Coupled Mult iprocessors
J. Gregory Steffan · Library and Archives Canada (Government of Canada) · 1997
To fully exploit the potential of single-chip multiprocessors, we must find a way to parallelize non-numeric applications. However, compilers have had little success in parallelizing nonnumeric codes due to their complex data access patterns. This paper explores the potential for using thread-level data speculation (TLDS) to overcome this limitation by allowing the compiler to view parallelization solely as a cost/benefit tradeoff, rather than something which may violate program correctness. Experimental results demonstrate that TLDS can offer significant program speedups. We also demonstrate that through modest hardware extensions, a standard singlechip multiprocessor could support TLDS by augmenting the cache coherence scheme to detect dependence violations, and by using the primary data caches to buffer speculative state. We quantify the impact of this implementation on performance, and we also evaluate the compiler support necessary to exploit TLDS. 1 Introduction As the number o...