A Memory-Centric Characterization of ASCI Applications Via a Combined Approach of Statistical and Empirical Analysis.
Xian‐He Sun, Kirk W. Cameron, Yong Cheng Luo, Dongmei He · 1999
Memory latency is a substantial contributor to single processor performance loss. Latency hiding techniques such as out of order and speculative execution, outstanding loads to memory, and increases in cache size, have been implemented by chip designers to alleviate this bottleneck. Incorporation of such techniques in superscalar processors has made application performance evaluation a more di cult task. Two recent, novel techniques are discussed � an empirical approach to modeling along with a statistical method are provided o ering insight to the memory latency problem. Combining the positive aspects of both analyses is a logical step toward providing a comprehensive picture of the e ectiveness of common latency hiding techniques. We provide this new combined method along with results in the context of computational physics workloads common to the ASCI (Accelerated Strategic Computing Initiative) project currently in progress at Los Alamos National Laboratory. The testbed used consists of the SGI Origin 2000 and the SGI PowerChallenge due to their use of the same RISCbased MIPS R10000 processor with di erent memory hiearchy implementations. Our goal is to o er a straight-forward approach toward quantifying the actual e ect of available latency hiding techniques based on results obtained from "on-chip " hardware performance counters. 1