Application of novel hierarchical approach to formal verification of digital ICs
Fatma A. El-Licy, H.S. Abdel-Aty-Zohdy · 2006
A hierarchical approach for the abstraction of digital VLSICs is presented. Circuit layout is hierarchically abstracted into logical constructs of binary tree structures, which may be manipulated to extract circuit functionality for the purpose of verifying design correctness. VLSIC design specification in the form of HDL is hierarchically decomposed to generate logical formulae for the given specification. By comparing the above, a verification report is obtained