The Renaissance-a residue number system based vector co-processor for DSP dominated embedded ASICs
Manish Bhardwaj, B. Ljusanin · 2002
This paper reports our ongoing investigation of a new paradigm to realize high performance DSP architectures suitable for embedded ASICs. The reasons for the significant gap between achievable MAC bandwidth and that delivered by current embedded DSP architectures are analyzed in detail. A processing engine composed of a general purpose DSP core closely coupled with an application-specific version of Renaissance-our previously developed vector co-processor with a residue arithmetic datapath-is proposed as a solution to close this gap. In the first step, code transformations are applied to firmware to expose the vector-like nature of DSP computation. Then, Renaissance's instruction set, datapath and control are personalized for vector primitives thus exposed. The most important advantages of this approach are that it is highly amenable to automation, it captures most of the compute intensive routines (>70%) quite well and makes the Renaissance reusable across applications. This paradigm has resulted in throughput gains ranging from 33% to over 200% when firmware for actual communications and speech coding applications was recoded. In Ren-AC, a Renaissance version optimized for a modem bank application, the system-wide increase in MAC throughput was higher than 50%.