The implementation of the next-generation 64 b Itanium/sup TM/ microprocessor
Samuel Naffziger, Glenn Edward Hammond · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003
The authors present the 64 bit Itanium/spl trade/ microprocessor, which incorporates over 220M transistors on a 465 mm/sup 2/ die and operates at >1.2 GHz with an 8-stage pipeline in a 0.18 /spl mu/m process. It has three levels of on-chip cache totaling over 3.3 MB providing >32 GB/s bandwidth at each level.