A 50 MHz 16-point FFT processor for WLAN applications
Neil H. E. Weste, M.A. Bickerstaff, T. Arivoli, Philip J. Ryan, John Dalton, David J. Skellern, T.M.P. Percival · 2002
This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 /spl mu/m TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.