FA 18.4: a phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane
Elias Reese, H. Wilson, D. Nedwek, J. Jex, Manpreet Khaira, T. Burton, P.V. Sunil Nag, H. Kumar, Charles Chimezie Dike, David Finan, M. Haycock · 2002
Recent parallel processor supercomputer designs use an active backplane of routers to form the interconnections between processing elements. Today, high-bandwidth interconnect systems capable of scaling to configurations with more than 500 processing nodes tend to use self-timed designs. This avoids clock distribution problems seen in large phase-sensitive synchronous systems. The BiCMOS routing component described in this paper employs 200 MHz clocked communication for large scalable parallel-processor supercomputer systems. This scheme eliminates need for clock edges to be phase-aligned across the clock distribution network. Additionally, router inputs accept data at any phase relationship to the receiving router internal clock.>