A 4.5 mm/sup 2/ multiplier array for a 200 MFLOP pipelined coprocessor
C. Heikes · 2002
This multiplier array is used in the floating point coprocessor that is part of several PA-RISC processor chips. This coprocessor is single- and double-precision IEEE compliant and is implemented in a 3-level-metal 0.8 /spl mu/m CMOS process. The floating point unit is comprised of a pipelined ALU, a pipelined multiplier, a divide and square-root unit, a 32/spl times/64 b register file and a control unit. Each of these units operates independently, allowing concurrent operations. The latency is nominally 20 ns for addition, multiplication and data conversions with a new issue every 10 ns. The latency of a single-precision divide or square-root is 80 ns.>