Different IO standard based energy efficient decoder design for 64-bit processor architecture
Shivani Madhok, Amanpreet Kaur, Bishwajeet Pandey · International Conference on Computing for Sustainable Global Development · 2015
In this work, our focus is on study and analysis of various IO standards at different temperatures. Virtex-6 is 40-nm FPGA and Kintex7 is 28-nm FPGA on which we implement our circuit to re-assure power reduction in sequential circuit. We have calculated power dissipation of different IO standards and analysed its power. The percentage of reduction in power dissipation for 28-nm FPGA is 65.56% with LVCMOS. There are 58.20% reduction in power dissipation with LVDCI_DV2_18, 41.72% reduction in power dissipation with HSLVDCI_15, 41.96% reduction in power dissipation with HSTL_I, 46.23% reduction in power dissipation with SSTL15, 60.83% reduction in power dissipation with LVDCI_DV2_15 when we use 28nm FPGA and temperature is scale down from 70 degree Celsius to 40 degree Celsius. Our paper describes architecture of 64-bit decoder through Xilinx ISE software provides the better support for Kintex-7 FPGA and Virtex-6 FPGA. LVCMOS is low voltage complementary metal oxide semiconductor. LVDCI is low voltage digitally control impedance. HS stands for High Speed. HSTL is high speed transceiver logic and SSTL is stub series terminated logic.