An I/sub DDQ/ fault model to facilitate the design of built-in current sensor (BICSs)
Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee · 2002
In-this paper, we present an efficient and accurate I/sub DDQ/ fault modeling technique for digital CMOS circuit. Both the normal and faulty "current" behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is obtained. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.