A 35 μW 1.1 V gate array 8×8 IDCT processor for video-telephony
R. Rambaldi, A. Ugazzoni, R. Guerrieri · 2002
We have designed and fabricated a low power IC to perform the inverse 8/spl times/8 DCT transform according to the CCITT precision specifications, suitable for portable video communication devices. Several design techniques have been used to reduce the power, such as a fast algorithm, an architecture that can exploit input signal correlation, and large amount of parallelism. The chip is fabricated in a triple metal 0.5 /spl mu/m gate array CMOS technology. The maximum throughput is 400 Kpix/s at 1.1 V, and 27 Mpix/s at 3.3 V. The measured power consumption is 35 /spl mu/W for typical image sequences in color QCIF format at 10 frames/sec with a 1.1 V power supply, making this device ideal for low power portable applications.