ECL-CMOS logic LSI technology using 20 GHz latch with CMOS test circuits
S. Yabuki, A. Hayashi, Yūichi Itō, Toru Maruyama, Hiroyuki Okada, Mitsuo Usami, Keiichi Higeta, M. Hamamoto, Satoru Isomura · European Solid-State Circuits Conference · 1999
An ECL-CMOS LSI for computing and communication including 280k ECL gates and 1Mbit RAM is developed with Advanced CMOS ECL Technology, which uses seven layer metallization including copper damascene and SGI/U-Isolation with SOI wafer. Used latch with CMOS test circuits has 20GHz toggle frequency and highly detectable delay test is possible.