Test optimization of bus-structured SoCs using embedded processor
M.H. Tehranipour, Mehrdad Nourani, Seid Mehdi Fakhraie, C. Papachristou · 2003
Embedded processors are now widely used in system-on-chips. This paper presents an optimization technique for testing a bus-structured system using an embedded processor.We present a systematic approach for test access mechanism that allows processor to access all cores with minimum overhead. We show an ILP formulation to minimize the test schedule. The method requires negligible overhead but provides great flexibility in terms of access mechanism and future reuse.