Architecture design of MPEG-2 decoder system
Yung-Pin Lee, Liang‐Gee Chen, Chung-Wei Ku · 2005
An architecture for the VLSI design of an MPEG-2 video decoder is introduced to achieve the MP@ML (main profile, main level). The hardware complexity is analyzed, and the decoding unit is designed to reach the required performance. The decoding unit includes variable length decoding (VLD), inverse scan, inverse quantization (IQ), IDCT, and motion compensation.