A 90 mW MPEG4 video codec LSI with the capability for core profile
T. Hashimoto, S. Kuromaru, Michihito Matsuo, K. Yasuo, T. Mori-iwa, Katsumichi Ishida, Satoshi Kajita, Masaharu Ohashi, M. Toujima, Tsuyoshi Nakamura, M. Hamada, T. Yonezawa, TERUHIKO KONDO, Kaito Hashimoto, Yuta Sugisawa, Hiroki Otsuki, M. Arita, H. Nakajima, H. Fujimoto, J. Michiyama · 2002
A single-chip MPEG4 video codec LSI with 20 Mb embedded DRAM performs a QCIF 15 Hz H.263 codec, a Simple at L1 codec, and Core at L1 decoding. It consumes 90 mW at 54 MHz. This chip integrates a programmable DSP, 8 dedicated hardware engines, and interface units on a 75.68 mm/sup 2/ die using 0.18 /spl mu/m 1.8 V quad-metal CMOS technology.