RDRAM/spl reg/ channel design with 32-bit 4.8 GB/s memory modules
Ching-Chao Huang, David Nguyen, Kyung Suk Oh, Wai-Yeung Yip, Dave Secker · Electrical Performance of Electronic Packaging · 2003
This paper describes an RDRAM channel design with novel 32-bit RIMM/spl reg/ modules which deliver a data bandwidth of 4.8 GB/s at 600-MHz clock frequency. Only two RIMM modules are needed for the entire 32-bit, 2-channel design, reducing both the board space and manufacturing cost. Detailed physical architecture, design optimization, and modeling and simulation methodology are presented. Numerous simulations with multi-stage calibration are automated to ensure ample voltage and timing margins for a robust design.