Reconfigurable implementation of bit-parallel multipliers over GF(2/sup m/) for two classes of finite fields
José Luis Imaña · 2005
Galois fields GF(2/sup m/) are used in a wide number of applications such as cryptography, digital signal processing and error-control codes. The multiplication is considered the most important and one of the most complex GF(2/sup m/) operations, so efficient multiplier architectures are highly desired. A new construction method of bit-parallel multipliers over GF(2/sup m/) for two classes of finite fields is presented. Our approach determines groups of subexpressions that can be shared among the product coordinates. General expressions are given, and the theoretical complexity analysis proves that our multipliers reduce the best time complexities known to date. The multipliers have been implemented on Xilinx Virtex FPGAs. The experiments prove that our method reduces the area requirements of the multipliers with respect to other similar multipliers.