On the fault location in combinational logic circuits
Rochit Rajsuman, Mohamed Saad, B. Gupta · 2002
A method is presented to identify and locate a fault in combinational logic circuits. A test pattern generator (called SPARK) has been developed, based on a modified version of the D-algorithm. A fault dictionary is set up during test generation. Through simulation, all activated lines under a test vector are identified. The test response is evaluated to identify possible paths which may have the fault. One does not stop testing as soon as a fault is detected. Based on circuit topology, the circuit is further exercised using fan-in and fan-out points to identify a faulty line segment or a gate. The fault location algorithm and experimental results on some combinational circuits are given.>