Design and analysis of ALU: Vedic mathematics approach
Garima Rawat, Khyati Rathore, Siddharth Goyal, Shefali Kala, Poornima Mittal · 2015
This paper presents a technique called “Vedic Mathematics” for designing the multiplier that is fast as compared to other multipliers based on mathematical techniques that have been in practice for a long time. A processor's speed depends prominently on its multiplier as multipliers are used in various fields where processing of some signal is essential. Here, a high-speed 8×8 bit multiplier is designed and analyzed which is based on the Vedic multiplier mechanism. This architecture is diverse from the conservative method of employing product of two numbers accomplished by the process of add and shift. The proposed method is efficient and fast, wherein the processing involves the vertical and crossed multiplication of precedent Vedic mathematics. It incorporates the partial products followed by additive result that too in a single step. The method and architecture decreases the complexity of the design of multiplier. The projected Vedic multiplier is coded in a high level digital language (VHDL) followed by synthesization using EDA tool, XilinxISE12.2i. Finally, a comparison is made between results based on Vedic methodology and stereotyped multipliers. Surprisingly, the performance is found superior in terms of delay and thereby efficiency too. Since, Vedic mathematics technique exhibits low time processing thereby the present work will be helpful in preceding a step towards high speed multipliers and processors.