Scheduling Driven Partitioning of Heterogeneous Embedded Systems
Paul Pop, Petru Eles, Zebo Peng · 2003
In this paper we present an algorithm for system level hardware/software partitioning of heterogeneous embedded systems. The system is represented as an abstract graph which captures both data-flow and the flow of control. Given an architecture consisting of several processors, ASICs and shared busses, our partitioning algorithm finds the partitioning with the smallest hardware cost and is able to predict and guarantee the performance of the system in terms of worst case delay. 1 Introduction A great deal of research has been done on hardware/software partitioning [1]. Several research groups consider hardware/software architectures consisting of a single programmable processor and an ASIC. In this case, the behaviour is partitioned into one software partition and one hardware partition. However, for complex systems, such a restricted architecture doesn't allow an efficient design space exploration, and therefore we will concentrate on more general architectures. As the predictability...