Comparison of two leading algorithms for PLA test pattern generation
R. Reilova, R. Valentin · 2002
The problem of fault test generation for programmable logic arrays (PLAs) is considered. The physical device faults are viewed in terms of their effect on the logical changes of the product terms constituting the PLA. Of the four possible logical faults: growth, shrinkage, appearance and disappearance; growth fault detection and test generation are investigated. The Bose and PLAtano algorithms for generating the single-fault growth test vectors are evaluated for efficiency, generality of solution, and ease of implementation.