Energy optimization of LDPC decoder circuits with timing violations
François Leduc-Primeau, Frank R. Kschischang, Warren J. Gross · 2015
This paper presents a quasi-synchronous design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware compensation mechanism. A quasi-synchronous low-density parity-check decoder processing circuit based on the offset min-sum algorithm is designed, achieving the same performance and occupying the same area as a conventional synchronous circuit, but using up to 28% less energy.