A memory efficient 3-D DWT architecture
Bijit Kumar Das, Swapna Banerjee · 2003
This paper proposes a memory efficient real-time 3-D DWT algorithm and its architectural implementation. As the running 3D-DWT refreshes the wavelet coefficients with the arrival of every two new frames, the latency of the conventional 3D-DWT reduces by at least 1/4 times. For realization of the transform canonical signed digit multiplier has been used. Parallelism being an added advantage for fast processing has been used with three pipelined stages in this architecture. For coefficient mapping, correlation between LPF and HPF in orthogonal Daubechies wavelet filter has been used. In this design the memory requirement has been optimized to the order O(KN/sup 2/ + (K - 2) /spl times/ N). The proposed architecture has been implemented on Xilinx FPGA devices at an operating frequency of 75 MHz. This low complexity architecture ensures 100% hardware utilization.