A 2K × 9 dual port memory
Frederick Lee Barber, David S Eisenberg, G A Ingram, M. Strauss, T.R. Wik · 1985
A 2K×9 CMOS dual port RAM linking asynchronous data between processor systems will be reported. Memory provides separate access ports and internally resolves conflicting access requests. Circuit combines a timed shared CMOS SRAM with logic to achieve a contention-induced error rate of less than 100 FITS.