Real‐Time Disparity Estimation Engine for High‐Definition 3 DTV Applications
Yu‐Cheng Tseng, Tian‐Sheuan Chang · 2013
This chapter proposes a hardware-efficient disparity estimation algorithm and its VLSI design to generate high-quality disparity maps and meet the real-time throughput of HD 3DTV. The main contributions of this chapter are as follows: At the algorithm level, for the high computation due to the HD frame size, the chapter first downsamples the computation of matching cost to generate a low-resolution disparity map and upsample it to a high-resolution one. Secondly, for the high memory cost due to the framelevel optimization, it proposes a hardware-efficient diffusion method that only requires the memory of two frame rows. Thirdly, the chapter proposes a no-motion registration (NMR) and stilledge preservation (SEP) method for temporal consistency, and intra/inter occlusion handling for disparity refinement. At the architecture level, it discusses a three-stage pipelining architecture and efficient processing elements (PEs) design for a high-throughput disparity estimation engine to achieve a throughput of HD1080p@95fps. Controlled Vocabulary Terms high definition television; Neuromorphics