A mainframe processor in CMOS technology with 0.5 mu m channel length
Helmut Schettler, Johann Hajdu, Klaus Getzlaff, W. Loehlein, C.W. Starke · 1990
A prototype of a processor chip set with a mainframe architecture is implemented using five CMOS standard cell chips. High performance is achieved by wide buses and a RISC- (reduced-instruction-set-computer) like implementation of frequently used instructions. The chip set consists of four units: (1) an instruction processor chip which fetches and decodes the instructions and contains the microcode storage; (2) cache chips which contain the address translation for up to 19 virtual address spaces, a four-way set-associative 16-kByte data/instruction cache, and a 32-B instruction buffer, which is loaded 16 B/cycle from the cache; (3) a fixed-point processor chip which contains the fixed-point registers and arithmetic and a second adder for the address calculation (base+displacement+index); (4) a floating-point processor chip which contains the floating-point registers, multiplier, and arithmetic unit. The processor is based on a four-stage pipeline (five stages for floating-point instructions).>