A hierarchical test access mechanism for SoC and the automatic test development flow
Chao-Wen Chou, Jing-Reng Huang, Ming-Jun Hsiao, Tsn-Yuan Chang · 2003
Testing of the SoC takes a noticeable percentage of the overall cost, while access to the embedded cores is one of the key points in testing. In this paper, a hierarchical test access architecture that can interact with P1500 and TAP is proposed, and a computer-aided automatic test integration flow is built. Based on the minimum five I/O pins, the core under test is linked by semi-direct path with the external ATE during testing. For the core integrator, test patterns from the core provider can be transferred into the embedded core. Thus, it dramatically reduces the test integration effort and shortens the testing development time. The experiment results show that the effective test time overhead is about 1%.