Reconfigurable ADC for 3-G UTRA-TDD mobile receiver
Alex Stojcevski, J. Singh, A. Zayegh · 2003
A novel reconfigurable architecture has been proposed for a mobile terminal receiver that can reduce power dissipation dependant on adjacent channel interference. Quantisation error analysis was carried out in order to find the minimum number of bits required. The proposed design can automatically scale the number of bits by monitoring the in-band and out-of-band powers. The new architecture performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. The UTRA-TDD downlink mode was examined statistically and results show that the reconfigurable architecture can save an average of up to 75% power dissipation when compared to a fixed word length of 16 bits. This will prolong talk and standby time in a mobile terminal. The average number of bits were calculated to be 10, for an outage of 97%.