A low memory FPGA based LDPC decoder architecture for quasi-cyclic LDPC codes
Paul Saunders, A.D. Fagan · 2006
We propose a novel low memory fully programmable FPGA decoder architecture to decode quasi-cyclic LDPC codes. By performing optimizations at the code construction, algorithmic and architecture levels we are able to achieve significant memory storage advantages over current FPGA decoder implementations. Our decoder employs the modified turbo decoding algorithm, to achieve a memory utilisation of 71 Kb using a Xilinx Virtex-4 device.