Low cost high performance bare die PoP with embedded trace coreless technology and “coreless cored” build up substrate manufacture process
Leilei Zhang, Joseph F. Greco · 2015
Handheld and mobile application processors are under high pressure of performance, form factor and cost. In this paper, we reviewed one high performance, low profile, low cost package on package (PoP) developed for NVIDIA's TK1 SOC. Detailed package special structure and unique substrate manufacture process flow are presented in this paper to explain how this package meets performance, form factor and cost challenges. This package also shows very robust reliability. No special toolings were needed for this package's handling, assembly process and surface mount process. Existing assembly line and SMT line were used for package manufacture and SMT. High layer count PoP products (8L and 7L coreless) have been designed with this technology. This product was successfully built and used in high performance handheld applications in high volume production Patents are in filling process.