Designing cad tools for reconfigurable computing
Majid Sarrafzadeh, Kiarash Bazargan · 2000
Advances in the FPGA technology, both in terms of device capacity and architecture, have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. To keep up with the ever-growing performance expectations of such systems, designers need new methodologies and tools for developing reconfigurable computing systems (RCS). New strategies should be devised in the design flow including compilation techniques, synthesis and physical design. In this work, we focus on devising fast high-level synthesis and physical design techniques to be employed in the compilation of programs to RCS platforms. We also present fast placement methods to be used in RCS runtime support systems. We have developed a tool that maps data flow graphs of the expressions in the loops of C programs to RCS platforms. Our proposed model provides RCS designers an integrated environment in which the user can control various parameters of the high-level and the device-specific stages of the design. The interaction between the high-level synthesis and the physical design phases not only makes the design process easier, but it also results in shorter design cycles. Also, comparing the placement speeds, by employing a hierarchical placement method before the FPGA vendor (Xilinx Design Manager in our experiments) place-and-route tool takes over the design process, we made the placeand-route cycle more than 2.5 times faster (the speedup for the Xilinx placement phase is 10.7 times on the average) only to lose 1.2 times in terms of the quality of the product. Such an approach is useful in the development cycle of applications for reconfigurable platforms, where a short compilation cycle is more desired than a fully optimized design. We also present a number of placement algorithms for dynamically reconfigurable computing systems. Some of our algorithms are applied at compile time, and some to be used as part of runtime support systems for RCS. Our placement algorithms provide a spectrum of speed/quality trade-offs. For example, for the online placement problem, we have showed that by giving up 6.89% the quality, we can gain about 5.14x speedup in the placement process.