The implementation of a 2-core multi-threaded itanium-family processor
Samuel Naffziger, Blaine Stackhouse, T. Grutkowski · 2005
The next generation in the Itanium/spl reg/ processor family, code named Montecito, is introduced. Implemented in a 90nm 7M process, the processor has two dual-threaded cores integrated with 26.5MB of cache. Of the total of 1.72B transistors, 64M are dedicated to logic and the rest to cache. With both cores operating at full speed, the chip consumes 100W.