An H.264/AVC Decoder with 4X4-Block Level Pipeline
Ting‐An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen‐Yi Lee · 2005
In this paper, we propose a 4/spl times/4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders, which adopt macroblock level pipelines, our proposed 4/spl times/4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260000 MB/s under 100 MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920/spl times/1088) video sequence in 30fps (244800 MB/s required) and level 4 of baseline profile.